AD1954YSTZ Datasheet, PDF (7/36 Pages) Analog Devices – SigmaDSP™ 3-Channel, 26-Bit Signal Processing DAC

AD1954
PIN FUNCTION DESCRIPTIONS
Pin No. Pin No.
Input/
(44-MQFP) (48-LQFP) Mnemonic Output Description*
1
NC
No Connect
1
2
MCLK2 IN
Master Clock Input 2 256 f_S/512 f_S
2
3
MCLK1 IN
Master Clock Input 1 256 f_S/512 f_S
3
4
MCLK0 IN
Master Clock Input 0 256 f_S/512 f_S
4
5
DEEMP/ IN
Enables 44.1 kHz De-emphasis Filter (Others Available through SPI Control)
SDATA_AUX
Auxiliary Serial Data Input
5
6
MUTE
IN
Mute Signal. Initiates volume ramp-down.
6
7
DVDD
Digital Supply for DSP Core, 4.5 V to 5.5 V
7
8
SDATA2 IN
Serial Data Input 2
8
9
BCLK2
IN
Bit Clock 2
9
10
LRCLK2 IN
Left/Right Clock 2
10
11
SDATA1 IN
Serial Data Input 1
11
12
BCLK1
IN
Bit Clock 1
12
13
DGND
Digital Ground
13
14
LRCLK1 IN
Left/Right Clock 1
14
15
SDATA0 IN
Serial Data Input 0
15
16
BCLK0
IN
Bit Clock 0
16
17
LRCLK0 IN
Left/Right Clock 0
17
18
CDATA
IN
SPI Data Input
18
19
CCLK
IN
SPI Data Bit Clock
19
20
CLATCH IN
SPI Data Framing Signal
20
21
RESETB IN
Reset Signal, Active Low
21
22
AVDD
Analog 5 V Supply
22
23
AGND
Analog GND
24
NC
No Connect
23
25
VOUTS– OUT Negative Sub Analog DAC Output
24
26
VOUTS+ OUT Positive Sub Analog DAC Output
25
27
AGND
Analog GND
26
28
VOUTR– OUT Negative Left Analog DAC Output
27
29
VOUTR+ OUT Positive Left Analog DAC Output
28
30
AVDD
Analog 5 V Supply
29
31
AGND
Analog GND
30
32
AVDD
Analog 5 V Supply
31
33
VOUTL+ OUT Positive Left Analog DAC Output
32
34
VOUTL– OUT Negative Left Analog DAC Output
33
35
AGND
Analog GND
36
NC
No Connect
37
NC
No Connect
34
38
VREF
IN
Connection for Filtered AVDD/2
35
39
FILTCAP IN
Connection for Noise Reduction Capacitor
36
40
ZEROFLAG OUT Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
37
41
SDATAOUT OUT Serial Data Mux Output
38
42
BCLKOUT OUT Bit Clock Mux Output
39
43
LRCLKOUT OUT Left/Right Clock Mux Output
40
44
ODVDD
Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V
41
45
DCSOUT OUT Data Capture Serial Output for Data Capture Registers. Use in conjunction with
selected LRCLK and BCLK to form a 3-wire output.
42
46
COUT
OUT SPI Data Output. Three-stated when inactive.
43
47
MCLKOUT OUT Master Clock Output 512 f_S/256 f_S (Frequency Selected by SPI Register)
44
48
DGND
Digital Ground
*For a complete description of the pins, refer to the Pin Functions section.
REV. A
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