AD1954YSTZ Datasheet, PDF (20/36 Pages) Analog Devices – SigmaDSP™ 3-Channel, 26-Bit Signal Processing DAC

AD1954
SPI Address
0–255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270–510
511
512–1024
Table II. SPI Port Address Decoding
Register Name
Read/Write Word Length
Parameter RAM
Write: 22 Bits
Read: 22 Bits
SPI Control Register 1
Write: 11 Bits
Read: 2 Bits
SPI Control Register 2
Write: 9 Bits
Read: N/A
Volume Left
Write: 22 Bits
Read: N/A
Volume Right
Write: 22 Bits
Read: N/A
Volume Sub
Write: 22 Bits
Read: N/A
Data Capture (SPI Out) #1
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: 24 Bits
Data Capture (SPI Out) #2
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: 24 Bits
Data Capture (Serial Out) Left
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Data Capture (Serial Out) Right
Write: 9-Bit Program Counter Value, 2-Bit Register Address
Read: N/A
Parameter RAM Safe Load Register 0
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Parameter RAM Safe Load Register 1
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Parameter RAM Safe Load Register 2
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Parameter RAM Safe Load Register 3
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Parameter RAM Safe Load Register 4
Write: 8-Bit Parameter RAM Address, 22-Bit Parameter Data
Read: N/A
Unused
Test Register
Write: 8 Bits
Read: N/A
Program RAM
Write: 35 Bits
Read: 35 Bits
SPI Address Decoding
Table II shows the address decoding used in the SPI port. The
SPI address space encompasses a set a registers and two RAMs,
one for holding signal processing parameters and one for hold-
ing the program instructions. Both of the RAMs are loaded on
power-up from on-board boot ROMs.
Control Register 1
Control Register 1 is an 11-bit register that controls data capture,
serial modes, de-emphasis, mute, power-down, and SPI-to-
memory transfers.Table III documents the contents of this register.
Table IV details the two bits in the register’s read operation.
Bits 1:0 set the word length, which is used in right-justified serial
modes to determine where the MSB is located relative to the start
of the audio frame.
Bits 3:2 select one of four serial modes, which are discussed in
the Serial Data Input Port section.
The de-emphasis curve selection Bits 5:4 turn on the internal
de-emphasis filter for one of three possible sample rates.
Bit 6, the soft power-down bit, stops the internal clocks to the DSP
core, but does not reset the part. The digital power consumption
is reduced to a low level when this bit is asserted. Reset can only
be asserted using the external reset pin.
Soft mute (Bit 7) is used to initiate a volume ramp-down sequence.
If the initial volume was set to 1.0, this operation will take 512
audio frames to complete.When this bit is de-asserted, a ramp-up
sequence is initiated until the volume returns to its original setting.
When set, Bit 8 enables the DCSOUT pin. This must be set in
order to read from the data capture serial out registers.
–20–
REV. A