TMS320C6711D_15 Datasheet, PDF (69/109 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6711D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS292B − OCTOBER 2005 − REVISED JUNE 2006
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN^{†‡§} (see Figure 22)
GDPA-167, ZDPA−167
–200
PLL MODE
BYPASS MODE
PLL MODE
BYPASS MODE
NO.
(PLLEN = 1)
(PLLEN = 0)
(PLLEN = 1)
(PLLEN = 0)
MIN MAX
MIN MAX
MIN MAX
MIN MAX
1 tc(CLKIN) Cycle time, CLKIN
6 83.3
6.7
5 83.3
6.7
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C
0.4C
0.4C
0.4C
3 tw(CLKINL) Pulse duration, CLKIN low
0.4C
0.4C
0.4C
0.4C
4 tt(CLKIN) Transition time, CLKIN
5
5
5
5
† _{The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.}
‡ _{C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.}
§ _{See the PLL and PLL controller section of this data sheet.}
UNIT
ns
ns
ns
ns
timing requirements for CLKIN^{†‡§} (see Figure 22)
–250
PLL MODE
BYPASS MODE
NO.
(PLLEN = 1)
(PLLEN = 0)
MIN MAX
MIN MAX
1 tc(CLKIN) Cycle time, CLKIN
4 83.3
6.7
2 tw(CLKINH) Pulse duration, CLKIN high
0.4C
0.4C
3 tw(CLKINL) Pulse duration, CLKIN low
0.4C
0.4C
4 tt(CLKIN) Transition time, CLKIN
5
5
† _{The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.}
‡ _{C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.}
§ _{See the PLL and PLL controller section of this data sheet.}
UNIT
ns
ns
ns
ns
CLKIN
1
4
2
3
4
Figure 22. CLKIN Timings
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