TMS320C6711D_15 Datasheet, PDF (27/109 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6711D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS292B − OCTOBER 2005 − REVISED JUNE 2006
Terminal Functions (Continued)
SIGNAL
NAME
PIN
NO.
GDP/
ZDP
TYPE†
IPD/
IPU‡
DESCRIPTION
HOST-PORT INTERFACE (HPI)
HINT
J20
O
IPU Host interrupt (from DSP to host)
HCNTL1
HCNTL0
G19
I
IPU Host control − selects between control, address, or data registers
G18
I
IPU Host control − selects between control, address, or data registers
HHWIL
H20
I
IPU Host half-word select − first or second half-word (not necessarily high or low order)
HR/W
HD15
HD14§
HD13§
HD12§
HD11
HD10
HD9
HD8§
HD7
HD6
HD5
HD4§
HD3§
G20
I
IPU Host read or write select
B14
IPU
Host-port data
• Used for transfer of data, address, and control
C14
IPU ^{• Also controls initialization of DSP modes at reset via pullup/pulldown resistors}
− Device Endian mode (HD8)
A15
IPU
0 – Big Endian
1 − Little Endian
C15
IPU
EMIF Big Endian mode correctness (EMIFBE) (HD12)
A16
IPU
0 – The EMIF data will always be presented on the ED[7:0] side of the bus,
regardless of the endianess mode (Little/Big Endian).
B16
IPU
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
present on the ED[7:0] side of the bus.
C16
IPU
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present
on the ED[31:24] side of the bus [default].
B17
IPU
I/O/Z
This new functionality does not affect systems using the curent default value of HD12=1. For
A18
IPU more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode
Correctness portion of this data sheet.
C17
IPU
− Bootmode (HD[4:3])
B18
IPU
00 – HPI boot/Emulation boot
01 − CE1 width 8-bit, Asynchronous external ROM boot with default timings
C19
IPD
(default mode)
10 − CE1 width 16-bit, Asynchronous external ROM boot with default timings
C20
IPU
11 − CE1 width 32-bit, Asynchronous external ROM boot with default timings
HD2
D18
HD1
D20
IPU _{Other HD pins (HD [15:13, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs/IPDs). For proper de-}
IPU ^{vice operation, do not oppose the HD [14, 13, 11:9, 7, 1, 0] pins with external pull−ups/pull-}
downs at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.
HD0
HAS
HCS
E20
IPU
For more details, see the Device Configurations section of this data sheet.
E18
I
IPU Host address strobe
F20
I
IPU Host chip select
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY^¶
HDS1
E19
I
IPU Host data strobe 1
HDS2
F18
I
IPU Host data strobe 2
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors}
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
§ _{To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-kΩ}
pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.
¶ _{To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.}
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