XIO2213BEVM Datasheet, PDF (68/201 Pages) Texas Instruments – PCI Express TO 1394b OHCI WITH 3-PORT PHY

XIO2213B
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
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4.35 Power Management Bridge Support Extension Register
This read-only register indicates to host software what the state of the secondary bus will be when the
bridge is placed in D3. See Table 4-21 for a complete description of the register contents.
PCI register offset: 56h
Register type:
Default value:
Read only
40h
BIT NUMBER
RESET STATE
76543210
01000000
Table 4-21. PM Bridge Support Extension Register Description
BIT
FIELD NAME
7
BPCC
6
BSTATE
5:0 RSVD
ACCESS
R
R
R
DESCRIPTION
Bus power/clock control enable. This bit indicates to the host software if the bus secondary
clocks are stopped when the bridge is placed in D3. The state of the BPCC bit is
controlled by bit 11 (BPCC_E) in the general control register (offset D4h, see
Section 4.66).
0 = Secondary bus clocks are not stopped in D3.
1 = Secondary bus clocks are stopped in D3.
B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.
Reserved. Returns 00 0000b when read.
4.36 Power Management Data Register
The read-only register is not applicable to the bridge and returns 00h when read.
PCI register offset:
Register type:
Default value:
57h
Read only
00h
BIT NUMBER
RESET STATE
76543210
00000000
4.37 MSI Capability ID Register
This read-only register identifies the linked list item as the register for message signaled interrupts
capabilities. The register returns 05h when read.
PCI register offset:
Register type:
60h
Read only
Default value:
05h
BIT NUMBER
RESET STATE
76543210
00000101
68
Classic PCI Configuration Space
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