XIO2213BEVM Datasheet, PDF (122/201 Pages) Texas Instruments – PCI Express TO 1394b OHCI WITH 3-PORT PHY

XIO2213B
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
www.ti.com
7.13 Power Management Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header
where the power-management register block resides. The OHCI controller configuration header double
words at offsets 44h and 48h provide the power-management registers. This register is read only and
returns 44h when read.
PCI register offset: 34h
Register type:
Default value:
Read only
44h
BIT NUMBER
RESET STATE
76543210
01000100
7.14 Interrupt Line and Interrupt Pin Registers
The interrupt line and interrupt pin registers communicate interrupt line routing information. See Table 7-10
for a complete description of the register contents.
PCI register offset:
Register type:
3Ch
Read/Write
Default value:
01FFh
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
BIT FIELD NAME
15-8 INTR_PIN
7-0 INTR_LINE
Table 7-10. Interrupt Line and Interrupt Pin Registers Description
TYPE
R
RW
DESCRIPTION
Interrupt pin. This field returns 01h when read, indicating that the 1394 OHCI core signals
interrupts on the INTA terminal.
Interrupt line. This field is programmed by the system and indicates to software which interrupt
line the OHCI controller INTA is connected to. The default value for this field is all FFh, indicating
that an interrupt line has not yet been assigned to the function.
122 1394 OHCI PCI Configuration Space
Submit Documentation Feedback
Product Folder Links: XIO2213B
Copyright © 2008–2013, Texas Instruments Incorporated