TMS320C5517_15 Datasheet, PDF (68/197 Pages) Texas Instruments – TMS320C5517 Fixed-Point Digital Signal Processor

TMS320C5517
SPRS727C – AUGUST 2012 – REVISED APRIL 2014
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5.7.2.3 Digital I/O Behavior When Core Power (CV_DD) is Down
With some exceptions (listed below), all digital I/O pins on the device have special features to allow
powering down of the Digital Core Domain (CV_DD) without causing I/O contentions or floating inputs at the
pins (see Figure 5-5). The device asserts the internal signal called HHV high when power has been
removed from the Digital Core Domain (CV_DD). Asserting the internal HHV signal causes the following
conditions to occur in any order:
• All output pin strong drivers to go to the high-impedance (Hi-Z) state
• Weak bus holders to be enabled to hold the pin at a valid high or low
• The internal pullups or pulldowns (IPUs and IPDs) on the I/O pins will be disabled
The exception pins that do not have this special feature are:
• Pins driven by the CV_DDRTC Power Domain [This power domain is "Always On"; therefore, the pins
driven by CV_DDRTC do not need these special features]:
– RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP
• USB Pins:
– USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO
• Pins for the Analog Block:
– GPAIN[3:0], DSP_LDO_EN, and BG_CAP
DVDD
Y
PAD
A
GZ
OR
HHV
hhvgz
HHV
PI
OR
HHV
hhvpi
Figure 5-5. Bus Holder I/O Circuit
NOTE
Figure 5-5 shows both a pullup and pulldown but pins only have one, not both.
PI = Pullup and Pulldown Inhibit
GZ = Output Enable (active low)
HHV = Described in Section 5.7.2.3
68
Specifications
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