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TMS320C5517_15 Datasheet, PDF (183/197 Pages) Texas Instruments – TMS320C5517 Fixed-Point Digital Signal Processor
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TMS320C5517
SPRS727C – AUGUST 2012 – REVISED APRIL 2014
6.4 Boot Modes
The device supports the following boot modes:
• NOR Flash
• NAND Flash
• SPI 16- and 24-bit EEPROM or Flash
• I2C 16-bit EEPROM
• eMMC Controller/MMC/SD/SDHC Card
• USB
• UART
• McSPI
• UHPI
The boot mode or method is determined by checking the value of the BootMode[5:0] bits in the BootMode
register ([1C34h]) and the CLKSELSTAT bit in the CCR2 register ([1C1Fh]), which reflect the
configurations of the EM_A[20:15] or GP[26:21] pins and CLK_SEL pin at reset. See Section 5.7.3.4.2,
BootMode Implementation and Requirements.
Figure 6-3. BootMode Register [1C34h]
15
11
10
5
4
0
Reserved
BootMode[5:0]
Reserved
R-0
R-EM_A[20:15]/GP[26:21]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:11
10:9
Name
Reserved
Table 6-33. BootMode Register Field Descriptions
Reserved
Description
BootMode[5:4]
Read-only bits that reflect the latched state of the EM_A[20:19] or GP[26:25] pins on the 10th clock
edge after RESET pin goes high.(1) The Bootloader reads this register value to determine the
frequency of the clock input to the system clock generator. The bootloader requires this frequency
to appropriately program the system clock generator and other peripheral clock dividers.
00:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 11.2896 MHz via the CLK_IN pin
01:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 12.00 MHz or 12.288 MHz via the CLK_IN pin
10:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 16.8 MHz via the CLK_IN pin
11:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 19.2 MHz via the CLK_IN pin
(1) The RESET pin is asynchronous to the selected system clock (CLKIN or USB_OSC). The pin could be 10, 11, or even 12 clock cycles
after the rising edge of RESETN due to possible metastability.
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