ADSP-21477KCPZ-1A Datasheet, PDF (65/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
OUTPUT DRIVE CURRENTS
Table 56 shows the driver types and the pins associated with
each driver. Figure 47 shows typical I-V characteristics for each
driver. The curves represent the current drive capability of the
output drivers as a function of output voltage.
Table 56. Driver Types
Driver Type
A
B
Associated Pins
FLAG[0–3], AMI_ADDR[23–0], DATA[15–0],
AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,
SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU,
TDO, RESETOUT, DPI[1–14], DAI[1–20],
WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO,
MLBCLK, SR_CLR, SR_LAT, SR_LDO[17–0],
SR_SCLK, SR_SDI
SDCLK, RTCLKOUT
200
150
TYPE B
V 3.13 V, 125 °C
OH
100
TYPE A
50
0
TYPE A
-50
-100
TYPE B
-150
V 3.13 V, 125 °C
OL
-200
0
0.5
1.0
1.5 2.0
2.5
3.0
3.5
SWEEP (V_DDEXT) VOLTAGE (V)
Figure 47. Typical Drive at Junction Temperature
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 21 on Page 29 through Table 55 on Page 64. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 48.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 49. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
V_LOAD
50:
70:
50:
4pF
2pF
400:
TESTER PIN ELECTRONICS
45:
0.5pF
T1
DUT
OUTPUT
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 48. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
INPUT
OR ^1.5V
OUTPUT
1.5V
Figure 49. Voltage Reference Levels for AC Measurements
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 48). Figure 52 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 50, Figure 51, and Figure 52 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
7
6
TYPE A DRIVE FALL
y = 0.0421x + 0.2418
TYPE A DRIVE RISE
y = 0.0331x + 0.2662
5
TYPE B DRIVE FALL
y = 0.0206x + 0.2271
4
3
TYPE B DRIVE RISE
y = 0.0184x + 0.3065
2
1
0
0
25
50
75
100 125 150 175 200
LOAD CAPACITANCE (pF)
Figure 50. Typical Output Rise/Fall Time (20% to 80%,
V_{DD_EXT} = Max)
Rev. C | Page 65 of 76 | July 2013