ADSP-21477KCPZ-1A Datasheet, PDF (56/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
SPI Interface—Master
Both the primary and secondary SPIs are available through DPI
only. The timing provided in Table 50 and Table 51 applies
to both.
Table 50. SPI Interface Protocol—Master Switching and Timing Specifications
88-Lead LFCSP Package All Other Packages
Parameter
Min
Max
Min
Max
Timing Requirements
t_SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) 10
8.6
t_HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
2
2
Switching Characteristics
t_SPICLKM
t_SPICHM
t_SPICLM
t_DDSPIDM
t_HDSPIDM
t_SDSCIM
t_HDSM
t_SPITDM
Serial Clock Cycle
8 × t_PCLK – 2
Serial Clock High Period
4 × t_PCLK – 2
Serial Clock Low Period
4 × t_PCLK – 2
SPICLK Edge to Data Out Valid (Data Out Delay time)
2.5
SPICLK Edge to Data Out Not Valid (Data Out Hold time)
DPI Pin (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to DPI Pin (SPI Device Select) High
Sequential Transfer Delay
4 × t_PCLK – 2
4 × t_PCLK – 2
4 × t_PCLK – 2
4 × t_PCLK – 2
8 × t_PCLK – 2
4 × t_PCLK – 2
4 × t_PCLK – 2
2.5
4 × t_PCLK – 2
4 × t_PCLK – 2
4 × t_PCLK – 2
4 × t_PCLK – 1.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
DPI
(OUTPUT)
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
t_SDSCIM
t_SPICHM
t_SPICLM
t_DDSPIDM
t_SSPIDM
t_HSPIDM
MOSI
(OUTPUT)
CPHASE = 0
t_SSPIDM
MISO
(INPUT)
t_HSPIDM
t_DDSPIDM
t_SPICLKM
t_HDSPIDM
t_HDSM
t_SPITDM
t_SSPIDM
t_HSPIDM
t_HDSPIDM
Figure 36. SPI Master Timing
Rev. C | Page 56 of 76 | July 2013