ADSP-21477KCPZ-1A Datasheet, PDF (49/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
Sample Rate Converter—Serial Input Port
The ASRC input signals are routed from the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided in
Table 41 are valid at the DAI_P20–1 pins.
Table 41. ASRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
t_SRCSFS1
Frame Sync Setup Before Serial Clock Rising Edge
4
ns
t_SRCHFS1
Frame Sync Hold After Serial Clock Rising Edge
5.5
ns
t_SRCSD1
Data Setup Before Serial Clock Rising Edge
4
ns
t_SRCHD1
Data Hold After Serial Clock Rising Edge
5.5
ns
t_SRCCLKW
Clock Width
(t_PCLK × 4) ÷ 2 – 1
ns
t_SRCCLK
Clock Period
t_PCLK × 4
ns
1 _{The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input}
can be either CLKIN or any of the DAI pins.
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
SAMPLE EDGE
t_SRCCLKW
t_SRCCLK
t_SRCSFS
t_SRCHFS
t_SRCSD
t_SRCHD
Figure 28. ASRC Serial Input Port Timing
Rev. C | Page 49 of 76 | July 2013