DAC5687-EP_15 Datasheet, PDF (61/76 Pages) Texas Instruments – 16-BIT 500-MSPS 2´–8´ INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5687-EP
www.ti.com
SGLS333 – JUNE 2006
Figure 71 and Figure 72 show the typical worst case spurious signal amplitudes vs f_DAC for a signal frequency
f_SIG = 11 × f_DAC/32 in each mode for PLL on (PLL clock mode) and PLL off (external and dual clock modes).
Each spurious signal (f_DAC/2, f_DAC/4 and f_DAC/8) has its own curve. The spurious signal amplitudes can then be
adjusted for the exact signal frequency f_SIG by applying the amplitude adjustment factor shown in Figure 73. The
amplitude adjustment factor is the same for each spurious signal (f_DAC/2, f_DAC/4, and f_DAC/8) and is normalize for
f_SIG = 11 × f_DAC/32.
(a) X2 Mode
90
(b) X4L Mode
100
80
90
70
f_DAC/2
60
50
40
30
20
80
70
f_DAC/4
60
50
f_DAC/2
40
30
20
10
10
0
0
100
200
300
400
500
fDAC − MHz
G032
0
0
100
200
300
400
500
fDAC − MHz
G033
(c) X4 Mode
100
(d) X8 Mode
100
90
90
80
80
f_DAC/4
f_DAC x 3/4
70
70
f_DAC/2
60
60
50
f_DAC/4
f_DAC x 3/4
40
50
f_DAC/2
f_DAC/8
40
f_DAC x 7/8
30
30
20
20
10
10
0
0
100
200
300
400
500
fDAC − MHz
G034
0
0
100
200
300
400
500
fDAC − MHz
G035
Figure 71. Clock Related Spurious Signal Amplitude With PLL Off for f_SIG = 11 × f_DAC / 32
Submit Documentation Feedback
61