DAC5687-EP_15 Datasheet, PDF (28/76 Pages) Texas Instruments – 16-BIT 500-MSPS 2´–8´ INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5687-EP
SGLS333 – JUNE 2006
Table 3. Coarse Mixer Sequences (continued)
invsinc:
cm_mode(3:0)
1000
Mixing Mode
f_DAC/4
1001
f_DAC/4
1010
f_DAC/4
1011
f_DAC/4
1100
–f_DAC/4
1101
–f_DAC/4
1110
–f_DAC/4
1111
–f_DAC/4
Enables the invsinc compensation filter when set.
Sequence
DAC A = {+A –B –A +B …}
DAC B = {+B +A –B –A …}
DAC A = {+A –B –A +B …}
DAC B = {–B –A +B +A …}
DAC A = {–A +B +A –B …}
DAC B = {+B +A –B –A …}
DAC A = {–A +B +A –B …}
DAC B = {–B –A +B +A …}
DAC A = {+A +B –A –B …}
DAC B = {+B –A –B +A …}
DAC A = {+A +B –A –B …}
DAC B = {–B +A +B –A …}
DAC A = {–A –B +A +B …}
DAC B = {+B –A –B +A …}
DAC A = {–A –B +A +B …}
DAC B = {–B +A +B –A …}
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Register Name: CONFIG3 — Address: 0x04, Default = 0x00
BIT 7
BIT 0
sif_4pin
dac_ser_data
half_rate
Unused
usb
0
0
0
0
0
counter_mode(2:0)
0
0
0
sif_4pin: Four-pin serial interface mode is enabled when set, 3-pin mode when cleared.
dac_ser_data: When set, both DAC A and DAC B input data is replaced with fixed data loaded into the 16 bit
serial interface ser_data register.
half_rate: Enables half-rate input mode. Input data for the DAC A data path is input to the chip at half speed
using both the DA(15:0) and DB(15:0) input pins.
usb:
When set, the data to DACB is inverted to generate upper side band output.
counter_mode(2:0): Controls the internal counter that can be used as the DAC data source.
{0XX = off; 100 = all 16b; 101 = 7b LSBs; 110 = 5b MIDs; 111 = 5b MSBs}
Register Name: SYNC_CNTL — Address: 0x05, Default = 0x00
BIT 7
BIT 0
sync_phstr
0
sync_nco
0
sync_cm
0
sync_fifo(2:0)
0
0
0
unused
0
unused
0
sync_phstr: When set, the internal clock divider logic is initialized with a PHSTR pin low-to-high transition.
sync_nco: When set, the NCO phase accumulator is cleared with a PHSTR low-to-high transition.
sync_cm: When set, the coarse mixer is initialized with a PHSTR low-to-high transition.
sync_fifo(2:0): Sync source selection mode for the FIFO. When a low-to-high transition is detected on the
selected sync source, the FIFO input and output pointers are initialized.
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