DAC5687-EP_15 Datasheet, PDF (55/76 Pages) Texas Instruments – 16-BIT 500-MSPS 2´–8´ INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

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Optional, May Be Bypassed
for Sine Wave Input
Swing Limitation
C_AC
0.1 µF
1:4
R_T
200 Ω
CLK
CLKC
Termination Resistor
S0029-01
Figure 63. Preferred Clock Input Configuration
DAC5687-EP
SGLS333 – JUNE 2006
TTL/CMOS
Source
R_opt
22 Ω
C_AC
0.01 µF
1:1
Optional, Reduces
Clock Feedthrough
CLK
CLKC
TTL/CMOS
Source
R_opt
22 Ω
0.01 µF
CLK
CLKC
Node CLKC Internally Biased
to CLKVDDń2
S0030-01
Figure 64. Driving the DAC5687 With a Single-Ended TTL/CMOS Clock Source
Differential ⁺
ECL
or
(LV)PECL
Source _–
R_T
130 Ω
R_T
130 Ω
R_T
82.5 Ω
R_T
82.5 Ω
C_AC
0.1 µF
C_AC
0.1 µF
100 Ω
CLK
CLKC
V_TT
S0031-01
Figure 65. Driving the DAC5687 With Differential ECL/PECL Clock Source
Power Up Sequence
In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or
simultaneously with PLLVDD. AVDD, CLKVDD, and IOVDD can be powered simultaneously or in any order.
Within AVDD, the multiple AVDD pins should be powered simultaneously.
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