TLK3101 Datasheet, PDF (6/24 Pages) Texas Instruments – 2.5 Gbps to 3.125 Gbps TRANSCEIVER

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649A – AUGUST 2000 – REVISED FEBRUARY 2001
transmit interface (continued)
high-speed data output
The high-speed data output driver consists of a voltage mode differential driver for a 50-Ω impedance
environment. The magnitude of the signal swing the differential driver pair is compatible with pseudo emitter
coupled logic (PECL) levels when ac-coupled. When ac-coupled the TLK3101 can interface to a PECL
transmitter and receiver. The line can be directly coupled or ac-coupled. Refer to Figure 18 and Figure 19 for
termination details.
The PECL outputs also provide pre-emphasis to compensating for ac loss when driving a cable or PCB
backplane over long distance (see Figure 3). The level of preemphasis is controlled by PREM as shown in
Table 2.
Table 2. Preemphasis Levels
PREM
PREEMPHASIS LEVEL (%)
(Vodp/Vodd –1)^†
0
5%
1
20%
† _{Vodp: Differential voltage swing when there is a}
transition in the data stream.
Vodd: Differential voltage swing when there is no
transition in the data stream.
VOD(p)
VOD(d)
Bit
Time
Bit
Time
VOD(p)
VOD(d)
Figure 3. Output Differential Voltage Under Preemphasis (|VTXP – VTXN|)
receive interface
The receiver portion of the TLK3101 accepts 8-b/10-b encoded differential serial data. The interpolator and
clock recovery circuit will lock to the data stream and extract the bit rate clock. This recovered clock is used to
retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-b/10-b
decoded and output on a 16 bit wide parallel bus synchronized to the extracted receive clock.
receive data bus
The receive bus interface drives 16 bit wide single-ended TTL parallel data at the RXD[0:15] pins. Data is valid
on the rising edge of RX_CLK when RX_DV/LOS is asserted high and RX_ER is deasserted low. The RX_CLK
is used as the recovered word clock. The data, enable and clock signals are aligned as shown in Figure 4.
Detailed timing information can be found in the TTL output switching characteristics table.
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