TLK3101 Datasheet, PDF (4/24 Pages) Texas Instruments – 2.5 Gbps to 3.125 Gbps TRANSCEIVER

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649A – AUGUST 2000 – REVISED FEBRUARY 2001
transmit interface
The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of GTX_CLK.
The data is then 8-b/10-b encoded, serialized, and transmitted sequentially over the differential high-speed I/O
channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times creating a bit
clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising
and falling edges of the bit clock providing a serial data rate that is 20 times the reference clock. Data is
transmitted LSB (TXD0) first. The transmitter also inserts commas at the beginning of the transmission for byte
synchronization.
transmit data bus
The transmit bus interface accepts 16 bit wide single-ended TTL parallel data at the TXD[0:15] pins. Data is valid
on the rising edge of GTX_CLK when TX_EN is asserted high and TX_ER is deasserted low. The GTX_CLK
is used as the word clock. The data, enable, and clock signals must be properly aligned as shown in Figure 1.
Detailed timing information can be found in the TTL input electrical characteristics table.
GTX_CLK
TXDn, TX_EN, TX_ER
tsu
th
Figure 1. Transmit Timing Waveform
transmission latency
The data transmission latency of the TLK3101 is defined as the delay from the initial 16-bit word load to the serial
transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process
variations and implementation variables such as supply voltage and temperature, the exact delay will vary
slightly. The minimum transmit latency (T_latency) is 34 bit times; the maximum is 38 bit times. Figure 2 illustrates
the timing relationship between the transmit data bus, GTX_CLK and serial transmit pins.
DOUTTXP,
DOUTTXN
TXD(0–15)
td(Tx _latency)
16 Bit Word to Transmit
Transmitted 20 Bit Word
GTX_CLK
Figure 2. Transmitter Latency
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