TICPAL22V10Z-25C Datasheet, PDF (6/22 Pages) Texas Instruments – EPICE CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

TICPAL22V10Z-25C, TICPAL22V10Z-30I
EPIC™ CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992
output logic macrocell (OLM) description
A great amount of architectural flexibility is provided by the user-configurable macrocell output options. The
macrocell consists of a D-type flip-flop and two select multiplexers. The D-type flip-flop operates like a standard
TTL D-type flip-flop. The input data is latched on the low-to-high transition of the clock input. The Q and Q outputs
are made available to the output select multiplexer. The asynchronous reset and synchronous set controls are
available in all flip-flops.
The select multiplexers are controlled by programmable cells. The combination of these programmable cells
will determine which macrocell functions are implemented. It is this user control of the architectural structure
that provides the generic flexibility of this device.
output logic macrocell diagram
From Clock Buffer
Output Logic Macrocell
MUX
2
AR
R
1D
C1
SS
1S
3
0
1
1
0
G
0
3
S0
MUX
1
1
G1
S1
AR = asynchronous reset
SS = synchronous set
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