TICPAL22V10Z-25C Datasheet, PDF (13/22 Pages) Texas Instruments – EPICE CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

TICPAL22V10Z-25C, TICPAL22V10Z-30I
EPIC™ CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992
PARAMETER MEASUREMENT INFORMATION
5V
From Output
Under Test
CL
(see Note A)
(see Note D)
S1
300 Ω
Test
Point
390 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
CLK
tsu
Data
Input
1.5 V
th
1.5 V
1.5 V
3V
0
3V
0
(see Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
tpd
In-Phase
Output
tpd
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
1.5 V
3V
1.5 V
0
tpd
VOH
1.5 V
VOL
tpd
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
High-Level
Pulse
1.5 V 1.5 V
tw
Low-Level
Pulse
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(low-level
enabling)
ten
1.5 V
tdis
1.5 V
Waveform 1
S1 Closed
(see Note C)
ten
Waveform 2
S1 Open
(see Note C)
1.5 V
tdis
1.5 V
3V
0
3V
0
(see Note B)
3V
0
(see Note B)
≈ 3.3 V
VOL + 0.5 V
VOL
VOH
VOH – 0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. All input pulses have the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr = tf = 2 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
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