THS7365 Datasheet, PDF (6/53 Pages) Texas Instruments – 6-Channel Video Amplifier with 3-SD and 3-HD Sixth-Order Filters and 6-dB Gain

THS7365
SBOS467 – MARCH 2009.................................................................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: V_S+ = +5 V (continued)
At T_A = +25°C, R_L = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7365
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AC PERFORMANCE (HD CHANNELS) (continued)
Return loss
f = 30 MHz, Filter mode
39
f = 1 MHz, HD to SD channels
–74
Crosstalk
f = 1 MHz, SD to HD channels
–78
f = 1 MHz, HD to HD channels
–70
DC PERFORMANCE
Biased output voltage
Input voltage range
V_IN = 0 V, SD channels
V_IN = 0 V, HD channels
DC input, limited by output
200
310
400
200
305
400
–0.1/2.3
Sync-tip clamp charge current
Input impedance
V_IN = –0.1 V, SD channels
V_IN = –0.1 V, HD channels
140
200
280
400
800 || 2
OUTPUT CHARACTERISTICS
High output voltage swing
Low output voltage swing
Output current (sourcing)
Output current (sinking)
POWER SUPPLY
R_L = 150 Ω to +2.5 V
R_L = 150 Ω to GND
R_L = 75 Ω to +2.5V
R_L = 75 Ω to GND
R_L = 150 Ω to +2.5 V (V_IN = –0.2 V)
R_L = 150 Ω to GND (V_IN = –0.2 V)
R_L = 75 Ω to +2.5 V (V_IN = –0.2 V)
R_L = 75 Ω to GND (V_IN = –0.2 V)
R_L = 10 Ω to +2.5 V
R_L = 10 Ω to +2.5 V
4.85
4.5
4.75
4.7
4.5
0.05
0.03
0.1
0.1
0.05
90
85
Operating voltage
2.6
5
5.5
V_IN = 0 V, all channels on
18
Total quiescent current, no load
V_IN = 0 V, SD channels on, HD channels off
6
V_IN = 0 V, SD channels off, HD channels on
12
V_IN = 0 V, all channels off, V_DISABLE = 3 V
Power-supply rejection ratio
(PSRR)
At dc
LOGIC CHARACTERISTICS⁽²⁾
21.6
28.5
7.2
9.5
14.4
19
1
10
52
V_IH
V_IL
I_IH
I_IL
Disable time
Disabled or Bypass engaged
Enabled or Bypass disengaged
2.1
2.2
0.8
0.8
0.2
0.2
80
Enable time
100
Bypass/filter switch time
5
TEST
UNITS LEVEL⁽¹⁾
dB
C
dB
C
dB
C
dB
C
mV
A
mV
A
V
C
µA
A
µA
A
kΩ || pF
C
V
C
V
A
V
C
V
C
V
C
V
A
V
C
V
C
mA
C
mA
C
V
B
mA
A
mA
A
mA
A
µA
A
dB
C
V
A
V
A
µA
C
µA
C
ns
C
ns
C
ns
C
(2) The logic input pins should not be left floating. They must be connected to logic low (or GND) or logic high (or V_S+).
6
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