STB13NK60Z_05 Datasheet, PDF (6/25 Pages) STMicroelectronics – N-CHANNEL 600V-0.48Ω-13A-TO-220/FP-D²/I²PAK-TO-247 Zener-Protected SuperMESH™ MOSFET

UCC1895
UCC2895
UCC3895
SLUS157L − DECEMBER 1999 − REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 µF,
CVDD = 0.1 µF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = −40°C to 85°C for UCC2895x and TA = 55°C to 125°C
for the UCC1895x. (unless otherwise noted)
PARAMETER
PWM COMPARATOR
tDELAY
EAOUT to RAMP input offset voltage
Minimum phase shift(2)
(OUTA to OUTC, OUTB to OUTD)
Delay(3)
(RAMP to OUTC, RAMP to OUTD)
IR(bias)
IR(sink)
RAMP bias current
RAMP sink current
TEST CONDITIONS
RAMP = 0 V,
DELAB=DELCD=REF
RAMP = 0 V
EAOUT = 650 mV
0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB=DELCD=REF
RAMP < 5 V,
CT = 2.2 V
RAMP = 5 V,
CT = 2.6 V
MIN TYP MAX UNITS
0.72 0.85 1.05 V
.0% .85% 1.4%
70 120 ns
−5
12
19
5 µA
mA
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
ADS
11
CS
12
CT
7
DELAB
9
DELCD
10
EAOUT
2
EAP
20
EAN
1
GND
5
OUTA
18
OUTB
17
OUTC
14
OUTD
13
PGND
16
RAMP
3
REF
4
RT
8
SS/DISB
19
SYNC
6
VDD
15
I/O
DESCRIPTION
I Adaptive delay set. Sets the ratio between the maximum and minimum programmed output delay dead time.
I Current sense input for cycle-by-cycle current limiting and for over-current comparator.
I
Oscillator timing capacitor for programming the switching frequency. The UCC3895’s oscillator charges CT
via a programmed current.
I
Delay programming between complementary outputs. DELAB programs the dead time between switching of
output A and output B.
I
Delay programming between complementary outputs. DELCD programs the dead time between switching of
output C and output D.
I/O Error amplifier output.
I Non-inverting input to the error amplifier. Keep below 3.6 volts for proper operation.
I Inverting input to the error amplifier. Keep below 3.6 volts for proper operation.
− Chip ground for all circuits except the output stages.
O
O _{The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits}
O ^{such as UCC27424 or gate drive transformers.}
O
− Output stage ground.
I Inverting input of the PWM comparator.
O
5 V, ±1.2%, 5 mA voltage reference. For best performance, bypass with a 0.1-µF low ESR, low ESL capacitor
to ground. Do not use more than 1.0 µF of total capacitance on this pin.
I Oscillator timing resistor for programming the switching frequency.
I Soft-start/disable. This pin combines the two independent functions.
I/O Oscillator synchronization. This pin is bidirectional.
I
Power supply input pin. VDD must be bypassed with a minimum of a 1.0-µF low ESR, low ESL capacitor to
ground. The addition of a 10−µF low ESR, low ESL between VDD and PGND is recommended.
6
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