MSP430G2X11_11 Datasheet, PDF (6/47 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430G2x11
MSP430G2x01
SLAS695D – FEBRUARY 2010 – REVISED FEBRUARY 2011
www.ti.com
Table 2. Terminal Functions
TERMINAL
NAME
NO.
14
16
N, PW RSA
P1.0/
TA0CLK/
ACLK/
2
1
CA0
P1.1/
TA0.0/
3
2
CA1
P1.2/
TA0.1/
4
3
CA2
P1.3/
CA3/
5
4
CAOUT
P1.4/
SMCLK/
CA4/
6
5
TCK
P1.5/
TA0.0/
CA5/
7
6
TMS
P1.6/
TA0.1/
CA6/
8
7
TDI/TCLK
P1.7/
CA7/
CAOUT/
9
8
TDO/TDI ⁽²⁾
XIN/
P2.6/
13
12
TA0.1
XOUT/
P2.7
12
11
RST/
NMI/
10
9
SBWTDIO
TEST/
SBWTCK
11
10
DVCC
1
16
DVSS
14
14
NC
-
15
QFN Pad
-
Pad
I/O
DESCRIPTION
General–purpose digital I/O pin
Timer0_A, clock signal TACLK input
I/O
ACLK signal output
Comparator_A+, CA0 input⁽¹⁾
General–purpose digital I/O pin
I/O Timer0_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input⁽¹⁾
General–purpose digital I/O pin
I/O Timer0_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input⁽¹⁾
General–purpose digital I/O pin
I/O Comparator_A+, CA3 input⁽¹⁾
Comparator_A+, output⁽¹⁾
General–purpose digital I/O pin
SMCLK signal output
I/O
Comparator_A+, CA4 input⁽¹⁾
JTAG test clock, input terminal for device programming and test
General–purpose digital I/O pin
Timer0_A, compare: Out0 output
I/O
Comparator_A+, CA5 input⁽¹⁾
JTAG test mode select, input terminal for device programming and test
General–purpose digital I/O pin
Timer0_A, compare: Out1 output
I/O
Comparator_A+, CA6 input⁽¹⁾
JTAG test data input or test clock input during programming and test
General–purpose digital I/O pin
CA7 input⁽¹⁾
I/O
Comparator_A+, output⁽¹⁾
JTAG test data output terminal or test data input during programming and test
Input terminal of crystal oscillator
I/O General–purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator⁽³⁾
I/O
General–purpose digital I/O pin
Reset
I Nonmaskable interrupt input
Spy–Bi–Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
I
Spy–Bi–Wire test clock input during programming and test
NA Supply voltage
NA Ground reference
NA Not connected
NA QFN package pad connection to V_SS recommended.
(1) MSP430G2x11 only
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection
to this pad after reset.
6
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