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CD74HC4059 Datasheet, PDF (6/7 Pages) Texas Instruments – High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter
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Test Circuits and Waveforms
CD74HC4059
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
trCL
CLOCK
INPUT
90%
10%
tH(H)
tfCL
50%
tH(L)
DATA
INPUT
tSU(H)
tSU(L)
OUTPUT
tREM
VCC
SET, RESET
OR PRESET
tTLH
90%
tPLH
50%
tTHL
90%
50%
10%
tPHL
IC
CL
50pF
VCC
GND
VCC
50%
GND
GND
FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL
TIME, AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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