CD74HC4059 Datasheet, PDF (3/7 Pages) Texas Instruments – High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

CD74HC4059
How to Preset the CD74HC/HCT4059 to Desired ÷N
The value N is determined as follows:
(EQ. 1)
N = (MODE†) (1000 x Decade 5 Preset + 100 x Decade 4
Preset + 10 x Decade 3 Preset + 1 x Decade 2 Preset) +
Decade 1 Preset
† MODE = First counting section divider (10, 8, 5, 4 or 2)
To calculate preset values for any N count, divide the N
count by the Mode. The resultant is the corresponding
preset values of the 5th through 2nd decade with the
remainder being equal to the 1st decade value.
Preset Value =
N
Mode
(EQ. 2)
Example:
Mode Select = 5
N = 8479, Mode = 5
K_a K_b K_c
HLH
1695 + 4 (Preset Values)
5 | 8479
Mode
N
4
1
J1 J2 J3 J4
L LH H
Program Jam Inputs (BCD)
5
9
J5 J6 J7 J8
H LH L
J9 J10 J11 J12
HLLH
6
J13 J14 J15 J16
LHHL
NOTE:
To verify the results, use Equation 1:
N = 5 (1000 x 1 + 100 x 6 + 10 x 9 + 1 x 5) + 4
N = 8479
12
GND
24
V_CC
J1 J2 J3 J4
345 6
PROGRAM JAM INPUTS (BCD)
J5 J6 J7 J8
J9 J10 J11 J12 J13 J14 J15 J16
22 21 20 19
18 17 16 15
PRESETTABLE LOGIC
10 9 8 7
P.E.
1
CLOCK
INPUT
FIRST
COUNTING
SECTION
÷10, 8, 5, 4, 2
INTERMEDIATE COUNTING SECTION
÷10
÷10
÷10
LAST
COUNTING
SECTION
÷1, 2, 2, 4, 8
RECOGNITION
GATING
MODE
SELECT
INPUTS
14
K_a
13
K_b
11
K_c
MODE
CONTROL
2
LATCH
ENABLE
PRESET
ENABLE
OUTPUT
STAGE
23
DIVIDE-BY-N
OUTPUT
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
3