CD74HC4059 Datasheet, PDF (5/7 Pages) Texas Instruments – High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

CD74HC4059
Prerequisite for Switching Specifications
PARAMETER
Pulse Width CP
Setup Time
K_b, K_c to CP
CP Frequency
SYMBOL V_CC (V) MIN
t_W
2
90
4.5
18
6
15
t_SU
2
75
4.5
15
6
13
f_MAX
2
5
4.5
27
6
32
25^oC
TYP
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-40^oC TO 85^oC
MIN TYP MAX
115
-
-
23
-
-
20
-
-
95
-
-
19
-
-
16
-
-
4
-
-
22
-
-
26
-
-
-55^oC TO 125^oC
MIN TYP MAX UNITS
135
-
-
ns
27
-
-
ns
23
-
-
ns
110
-
-
ns
22
-
-
ns
19
-
-
ns
4
-
-
MHz
18
-
-
MHz
21
-
-
MHz
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Propagation Delay,
CP to Q
t_PLH, t_PHL C_L = 50pF
2
-
- 200
-
250
-
300
ns
4.5 -
-
40
-
50
-
60
ns
6
-
- 34
-
43
-
51
ns
Propagation Delay,
LE to Q
C_L = 15pF
5
- 17 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
2
-
- 175
-
220
-
265
ns
4.5 -
-
35
-
44
-
53
ns
6
-
- 30
-
37
-
45
ns
Output Transition Time
C_L = 15pF
5
- 14 -
-
-
-
-
ns
t_THL, t_TLH C_L = 50pF
2
-
- 75
-
95
-
110
ns
4.5 -
-
15
-
19
-
22
ns
6
-
- 13
-
16
-
19
ns
CP Frequency
f_MAX
C_L = 15pF
5
- 54 -
-
-
-
-
MHz
Input Capacitance
C_I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 6, 7)
C_PD
-
5
- 36 -
-
-
-
-
pF
NOTES:
6. C_PD is used to determine the dynamic power consumption, per package.
7. P_D = C_PD V_CC2 f_i + Σ C_L V_CC2 f_o where f_i = input frequency, f_o = output frequency, C_L = output load capacitance, V_CC = supply voltage.
5