CD74HC373 Datasheet, PDF (6/9 Pages) Texas Instruments – High Speed CMOS Logic Octal Transparent Latch, Three-State Output

CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Output Enabling Time
SYMBOL
t_PZL, t_PZH
TEST
CONDITIONS V_CC (V)
C_L = 50pF
2
4.5
25^oC
-40^oC TO 85^oC
TYP MAX
MAX
-
150
190
-
30
38
-55^oC TO
125^oC
MAX
225
45
UNITS
ns
ns
6
-
26
33
38
ns
C_L = 15pF
5
12
-
-
Output Disabling Time
t_PLZ, t_PHZ C_L = 50pF
2
-
150
190
4.5
-
30
38
-
ns
225
ns
45
ns
6
-
26
33
38
ns
C_L = 15pF
5
12
-
-
Output Transition Time
t_TLH, t_THL C_L = 50pF
2
-
60
75
4.5
-
12
15
-
ns
90
ns
18
ns
6
-
10
13
15
ns
Input Capacitance
Three-State Output
Capacitance
C_I
-
-
-
10
10
C_O
-
-
-
20
20
10
pF
20
pF
Power Dissipation
Capacitance
(Notes 5, 6)
C_PD
-
5
51
-
-
-
pF
HCT TYPES
Propagation Delay,
Data to Qn
(HC/HCT373)
t_PLH, t_PHL C_L = 50pF
4.5
-
32
40
C_L = 15pF
5
13
-
-
48
ns
-
ns
Propagation Delay,
Data to Qn
(HC/HCT573)
t_PLH, t_PHL C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
17
-
-
53
ns
-
ns
Propagation Delay,
LE to Qn
t_PLH, t_PHL C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
14
-
-
Output Enabling Time
t_PZL, t_PZH C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
14
-
-
Output Disabling Time
t_PLZ, t_PZH C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
14
-
-
Output Transition Time
t_TLH, t_THL C_L = 50pF
4.5
-
12
15
Input Capacitance
C_I
-
-
-
10
10
Three-State Output
Capacitance
C_O
-
-
-
20
20
53
ns
-
ns
53
ns
-
ns
53
ns
-
ns
18
ns
10
pF
20
pF
Power Dissipation
Capacitance
(Notes 5, 6)
C_PD
-
5
53
-
-
-
pF
NOTES:
5. C_PD is used to determine the no-load dynamic power consumption, per latch.
6. P_D (total power per latch) = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
6