CD74HC373 Datasheet, PDF (2/9 Pages) Texas Instruments – High Speed CMOS Logic Octal Transparent Latch, Three-State Output

CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Pinout
CD74HC373, CD74HCT373
(PDIP, SOIC)
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V_CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
CD54HC573, CD74HC573, CD74HCT573
(PDIP, SOIC, CERDIP)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Functional Block Diagrams
CD74HC373, CD74HCT373, CD74HC573, CD74HCT573
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
D
GO
D
GO
D
GO
D
GO
D
GO
D
GO
D
GO
D
GO
LE
OE
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
CD74HCT573
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
LE
OE
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
OUTPUT
L
H
H
H
L
H
L
L
L
L
l
L
L
L
h
H
H
X
X
Z
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2