CD54HCT175_07 Datasheet, PDF(6/14 Page) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

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CD54HCT175_07 Datasheet, PDF (6/14 Pages) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

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CD54HC175, CD74HC175, CD54HCT175, CD74HCT175

Switching Speciï¬cations Input tr, tf = 6ns (Continued)

PARAMETER

HCT TYPES

Propagation Delay,

Clock to Q or Q

Propagation Delay,

MR to Q or Q

Output Transition Times

Input Capacitance

Power Dissipation

Capacitance

(Notes 3, 4)

TEST

SYMBOL CONDITIONS VCC (V)

tPLH, tPHL CL = 50pF

4.5

CL = 15pF

tPLH, tPHL CL = 50pF

4.5

CL = 15pF

tTLH, tTHL CL = 50pF

4.5

CIN

CPD

25oC

-40oC TO 85oC

TYP MAX

MAX

-55oC TO

125oC

MAX

UNITS

NOTES:

3. CPD is used to determine the dynamic power consumption, per flip-flop.

4. PD = VCC2 fi + â (CL VCC2 + fO) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

trCL

CLOCK

INPUT

90%

10%

tH(H)

tfCL

50%

tH(L)

DATA

INPUT

tSU(H)

tSU(L)

OUTPUT

tREM

VCC

SET, RESET

OR PRESET

tTLH

90%

tPLH

50%

tTHL

90%

50%

10%

tPHL

50pF

VCC

GND

VCC

50%

GND

trCL

CLOCK

INPUT

2.7V

0.3V

tfCL

1.3V

tH(H)

tH(L)

DATA

INPUT

tSU(H)

1.3V

tSU(L)

OUTPUT

tREM

SET, RESET

OR PRESET

tTLH

90%

1.3V

tPLH

1.3V

tTHL

90%

1.3V

10%

tPHL

50pF

GND

FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

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