CD54HCT175_07 Datasheet, PDF (1/14 Pages) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

Data sheet acquired from Harris Semiconductor
SCHS160C
August 1997 - Revised October 2003
CD54HC175, CD74HC175,
CD54HCT175, CD74HCT175
High-Speed CMOS Logic
Quad D-Type Flip-Flop with Reset
[ /Title
(CD74
HC175
,
CD74
HCT17
5)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
D-
Type
Flip-
Features
• Common Clock and Asynchronous Reset on Four
D-Type Flip-Flops
• Positive Edge Pulse Triggering
• Complementary Outputs
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Description
advantage of standard CMOS ICs and the ability to drive 10
LSTTL devices.
Information at the D input is transferred to the Q, Q outputs on
the positive going edge of the clock pulse. All four Flip-Flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All four Q outputs are reset to a
logic 0 and all four Q outputs to a logic 1.
Ordering Information
PART NUMBER
CD54HC175F3A
CD54HCT175F3A
CD74HC175E
CD74HC175M
CD74HC175MT
CD74HC175M96
CD74HCT175E
CD74HCT175M
CD74HCT175MT
CD74HCT175M96
TEMP. RANGE
(^oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
The ’HC175 and ’HCT175 are high speed Quad D-type Flip-
Flops with individual D-inputs and Q, Q complementary
outputs. The devices are fabricated using silicon gate CMOS
technology. They have the low power consumption
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC175, CD54HCT175
(CERDIP)
CD74HC175, CD74HCT175
(PDIP, SOIC)
TOP VIEW
MR 1
Q₀ 2
Q₀ 3
D₀ 4
D₁ 5
Q₁ 6
Q₁ 7
GND 8
16 V_CC
15 Q₃
14 Q₃
13 D₃
12 D₂
11 Q₂
10 Q₂
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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