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CD54HCT175_07 Datasheet, PDF (5/14 Pages) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset
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CD54HC175, CD74HC175, CD54HCT175, CD74HCT175
Prerequisite For Switching Specifications (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Setup Time, Data to Clock
tSU
-
2 80 -
-
100
-
120
-
ns
4.5 16 -
-
20
-
24
-
ns
6 14 -
-
17
-
20
-
ns
Hold Time, Data to Clock
tH
-
2
5
-
-
5
-
5
-
ns
4.5 5 -
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
Removal Time, MR to Clock
tREM
-
2
5
-
-
5
-
5
-
ns
4.5 5 -
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
Clock Frequency
fMAX
-
2
6
-
-
5
-
4
-
MHz
4.5 30 -
-
25
-
20
-
MHz
6 35 -
-
29
-
23
-
MHz
HCT TYPES
Clock Pulse Width
MR Pulse Width
Setup Time Data to Clock
Hold Time Data to Clock
Removal Time MR to Clock
Clock Frequency
tw
tw
tSU
tH
tREM
fMAX
-
4.5 20 -
-
25
-
30
-
ns
-
4.5 20 -
-
25
-
30
-
ns
-
4.5 20 -
-
25
-
30
-
ns
-
4.5 5 -
-
5
-
5
-
ns
-
4.5 5 -
-
5
-
5
-
ns
-
4.5 25 -
-
20
-
16
-
MHz
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay, Clock to
Q or Q
TEST
SYMBOL CONDITIONS VCC (V)
tPLH, tPHL CL = 50pF
2
4.5
25oC
-40oC TO 85oC
TYP MAX
MAX
-
175
220
-
35
44
-55oC TO
125oC
MAX
265
53
UNITS
ns
ns
6
-
30
37
45
ns
Propagation Delay,
MR to Q or Q
CL = 15pF
5
14
-
-
tPLH, tPHL CL = 50pF
2
-
175
220
4.5
-
35
44
-
ns
265
ns
53
ns
6
-
30
37
45
ns
CL = 15pF
5
14
-
-
Output Transition Times
tTLH, tTHL CL = 50pF
2
-
75
95
4.5
-
15
19
-
ns
110
ns
22
ns
6
-
13
16
19
ns
Input Capacitance
Power Dissipation
Capacitance
(Notes 3, 4)
CIN
-
-
-
10
10
CPD
-
5
65
-
-
10
pF
-
pF
5
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