CD54HC4040 Datasheet, PDF (6/15 Pages) Texas Instruments – High-Speed CMOS Logic 12-Stage Binary Counter

CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040
Prerequisite for Switching Specifications (Continued)
25^oC
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
Reset Removal Time
SYMBOL V_CC (V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
t_REM
2
50
-
65
-
75
-
ns
4.5
10
-
13
-
15
-
ns
6
9
-
11
-
13
-
ns
Reset Pulse Width
t_W
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
HCT TYPES
Maximum Input Pulse
Frequency
f_MAX
4.5
25
-
20
-
16
-
MHz
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
t_W
4.5
20
-
25
-
30
-
ns
t_REM
4.5
10
-
13
-
15
-
ns
t_W
4.5
20
-
25
-
30
-
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
25^oC
-40^oC TO
85^oC
-55^oC TO
125^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay
(Figure 1)
t_PLH, t_PHL C_L = 50pF
2
-
-
140
-
175
-
210
ns
CP to Q₁’ Output
Q_n to Q_n + 1
C_L =15pF
C_L = 50pF
t_PLH, t_PHL C_L = 50pF
4.5
-
-
28
-
35
-
42
ns
5
-
11
-
-
-
-
-
ns
6
-
-
24
-
30
-
36
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
MR to Q_n
C_L =15pF
C_L = 50pF
t_PLH, t_PHL C_L = 50pF
5
-
4
-
-
-
-
-
ns
6
-
-
13
-
16
-
19
ns
2
-
-
170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
5
-
14
-
-
-
-
-
ns
6
-
-
29
-
37
-
43
ns
Output Transition Time
(Figure 1)
t_TLH, t_THL C_L = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
Power Dissipation
Capacitance (Notes 3, 4)
C_IN
C_PD
C_L = 50pF
C_L =15pF
-
-
-
10
-
10
-
10
pF
5
-
40
-
-
-
-
-
pF
HCT TYPES
Propagation Delay
(Figure 1)
t_PLH, t_PHL C_L = 50pF
4.5
-
-
40
-
50
-
60
ns
CP to Q₁’ Output
C_L =15pF
5
-
17
-
-
-
-
-
ns
6