CD54HC174_08 Datasheet, PDF (6/14 Pages) Texas Instruments – High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset

CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
HCT TYPES
Propagation Delay, Clock to Q
Propagation Delay, MR to Q
Output Transition Times
Input Capacitance
Power Dissipation
Capacitance
(Notes 3, 4)
SYMBOL
t_PLH, t_PHL
t_PLH, t_PHL
t_TLH, t_THL
C_IN
C_PD
TEST
CONDITIONS V_CC (V)
C_L = 50pF
4.5
C_L = 15pF
5
C_L = 50pF
4.5
C_L = 15pF
5
C_L = 50pF
4.5
-
-
-
5
25^oC
TYP MAX
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
-
40
50
17
-
-
-
44
55
18
-
-
-
15
19
-
10
10
44
-
-
60
ns
-
ns
66
ns
-
ns
22
ns
10
pF
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per flip-flop.
4. P_D = V_CC2 f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_rC_L
CLOCK
INPUT
90%
10%
t_H(H)
t_fC_L
50%
t_H(L)
DATA
INPUT
t_SU(H)
t_SU(L)
OUTPUT
t_REM
V_CC
SET, RESET
OR PRESET
t_TLH
90%
t_PLH
50%
t_THL
90%
50%
10%
t_PHL
IC
C_L
50pF
V_CC
GND
V_CC
50%
GND
GND
t_rC_L
CLOCK
INPUT
2.7V
0.3V
t_fC_L
1.3V
t_H(H)
t_H(L)
DATA
INPUT
t_SU(H)
1.3V
1.3V
1.3V
t_SU(L)
OUTPUT
t_REM
3V
SET, RESET
OR PRESET
t_TLH
90%
1.3V
t_PLH
1.3V
t_THL
90%
1.3V
10%
t_PHL
IC
C_L
50pF
3V
GND
3V
GND
GND
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
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