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CD54HC174_08 Datasheet, PDF (5/14 Pages) Texas Instruments – High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset
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CD54HC174, CD74HC174, CD54HCT174, CD74HCT174
Prerequisite For Switching Function (Continued)
PARAMETER
Setup Time, Data to Clock
SYMBOL
tSU
TEST
CONDITIONS VCC (V)
-
2
4.5
25oC
MIN MAX
60
-
12
-
-40oC TO 85oC -55oC TO 125oC
MIN MAX MIN MAX UNITS
75
-
90
-
ns
15
-
18
-
ns
6
10
-
13
-
15
-
ns
Hold Time, Data to Clock
tH
-
2
5
-
5
-
5
-
ns
4.5
5
-
5
-
5
-
ns
6
5
-
5
-
5
-
ns
Removal Time, MR to Clock
tREM
-
2
5
-
5
-
5
-
ns
4.5
5
-
5
-
5
-
ns
6
5
-
5
-
5
-
ns
Clock Frequency
fMAX
-
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
HCT TYPES
Clock Pulse Width
MR Pulse Width
Setup Time, Data to Clock
Hold Time, Data to Clock
Removal Time, MR to Clock
Clock Frequency
tw
tw
tSU
tH
tREM
fMAX
-
4.5
20
-
25
-
30
-
ns
-
6
25
-
31
-
38
-
ns
-
4.5
16
-
20
-
24
-
ns
-
6
5
-
5
-
5
-
ns
-
4.5
12
-
15
-
18
-
ns
-
6
25
-
20
-
17
-
MHz
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay, Clock to Q
SYMBOL
tPLH, tPHL
TEST
CONDITIONS VCC (V)
CL = 50pF
2
4.5
25oC
TYP MAX
-40oC TO 85oC -55oC TO 125oC
MAX
MAX
UNITS
-
165
205
-
33
41
250
ns
50
ns
6
-
28
35
43
ns
CL = 15pF
5
13
-
-
Propagation Delay, MR to Q tPLH, tPHL CL = 50pF
2
-
150
190
4.5
-
30
38
-
ns
225
ns
45
ns
6
-
26
33
38
ns
CL = 15pF
5
12
-
-
Output Transition Times
tTLH, tTHL CL = 50pF
2
-
75
95
4.5
-
15
19
-
ns
110
ns
22
ns
6
-
13
16
19
ns
Input Capacitance
Power Dissipation
Capacitance
(Notes 3, 4)
CIN
CPD
-
-
-
10
10
-
5
38
-
-
10
pF
-
pF
5
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