ADS6425 Datasheet, PDF (6/56 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6425
SLWS197 – MARCH 2007
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD =
LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode
(unless otherwise noted).
THD
ENOB
IMD
PARAMETER
TEST CONDITIONS
MIN
Fin = 10 MHz
Fin = 50 MHz
70
Total harmonic distortion
Fin = 100 MHz
Fin = 170 MHz
Fin = 230 MHz
Effective number of bits
Fin = 50 MHz
10.8
F1= 46.09 MHz, F2 = 50.09 MHz
Two-tone intermodulation distortion
F1= 185.09 MHz, F2 = 190.09 MHz
Cross-talk
Near channel, Frequency of interfering signal
= 10 MHz
Far channel, Frequency of interfering signal
= 10 MHz
TYP MAX UNIT
88
81
84
dBc
73
72
11.4
Bits
90
dBFS
82
92
dBFS
105
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3V, I_O = 3.5mA, R_LOAD = 100Ω⁽¹⁾.
All LVDS specifications are characterized, but not tested at production.
PARAMETER
DIGITAL INPUTS
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
DIGITAL OUTPUTS
High-level output voltage
Low-level output voltage
|V_OD| Output differential voltage
V_OS Output offset voltage
Output capacitance
TEST CONDITIONS
Common-mode voltage of OUTP and OUTM
Output capacitance inside the device, from either output to
ground
MIN TYP MAX UNIT
2.4
10
10
4
V
0.8 V
µA
µA
pF
1375
mV
1025
mV
250 350 450 mV
1200
mV
2
pF
(1) I_O refers to the LVDS buffer current setting, R_LOAD is the external differential load resistance between the LVDS output pair
6
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