ADS6425 Datasheet, PDF (1/56 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6425
www.ti.com
SLWS197 – MARCH 2007
QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE
FEATURES
• Maximum Sample Rate: 125 MSPS
• 12-Bit Resolution with No Missing Codes
• 1.65-W Total Power
• Simultaneous Sample and Hold
• 70.3 dBFS SNR at Fin = 50 MHz
• 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
• 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
• 3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
• Serialized LVDS Outputs with Programmable
Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
Clock Inputs and Amplitude Down to 400 mV_pp
differential
• Internal Reference with External Reference
Support
• No External Decoupling Required for
References
• 3.3-V Analog and Digital Supply
• 64 QFN Package (9 mm × 9 mm)
• Pin Compatible 14-Bit Family (ADS644X)
APPLICATIONS
• Base-station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment
DESCRIPTION
The ADS6425 is a high performance 12-bit,
125-MSPS quad channel ADC. Serial LVDS data
outputs reduce the number of interface lines,
resulting in a compact 64-pin QFN package (9 mm ×
9 mm) that allows for high system integration density.
The device includes 3.5 dB coarse gain option that
can be used to improve SFDR performance with little
degradation in SNR. In addition to the coarse gain,
fine gain options also exist, programmable in 1dB
steps up to 6dB.
The output interface is 2-wire, where each ADC's
data is serialized and output over two LVDS pairs.
This makes it possible to halve the serial data rate
(compared to a 1-wire interface) and restrict it to less
than 1Gbps easing receiver design. The ADS6425
also includes the traditional 1-wire interface that can
be used at lower sampling frequencies.
An internal phase locked loop (PLL) multiplies the
incoming ADC sampling clock to derive the bit clock.
The bit clock is used to serialize the 12-bit data from
each channel. In addition to the serial data streams,
the frame and bit clocks are also transmitted as
LVDS outputs. The LVDS output buffers have
features such as programmable LVDS currents,
current doubling modes and internal termination
options. These can be used to widen eye-openings
and improve signal integrity, easing capture by the
receiver.
The ADC channel outputs can be transmitted either
as MSB or LSB first and 2s complement or straight
binary.
ADS6425 has internal references, but can also
support an external reference mode. The device is
specified over the industrial temperature range
(–40°C to 85°C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated