ADS6425 Datasheet, PDF (10/56 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6425
SLWS197 – MARCH 2007
www.ti.com
Table 2. Priority Between Parallel Pins and Serial Registers
PIN
CFG1 to
CFG4
PDN
SEN
SCLK,
SDATA
FUNCTIONS SUPPORTED
As described in Table 6 to
Table 9
Global power down
Serial Interface Enable
Serial Interface Clock and
Serial Interface Data
PRIORITY
Register bits can control the modes ONLY if the <OVRD> bit is high. If the <OVRD> bit is
LOW, then the control voltage on these parallel pins determines the function as per Tables
D0 bit in register 0x00 controls global power down ONLY if PDN pin is LOW. If PDN is high,
device is in global power down mode.
3.5 dB coarse gain setting is controlled by bit D5 in register 0x0D ONLY if the <OVRD> bit is
high. Else, it is in default setting of 0 dB coarse gain.
Internal/External reference setting is determined by bit D5 in register 0x00.
Bits D5-D7 in register 0x0A control the SYNC and DESKEW output patterns.
Power down is determined by bit D0 in 0x00 register.
AVDD
3R
(5/8) AVDD
2R
(3/8) AVDD
3R
GND
(5/8) AVDD
GND
AVDD
(3/8) AVDD
To Parallel Pin
Figure 3. Simple Scheme to Configure Parallel Pins
10
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