ADS6149_1 Datasheet, PDF (6/69 Pages) Texas Instruments – 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs

ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS – ADS614X and ADS612X
Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal
reference mode unless otherwise noted.
Min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V
PARAMETER
ADS6149/ADS6129
250 MSPS
MIN TYP MAX
ADS6148/ADS6128
210 MSPS
MIN TYP MAX
UNIT
ANALOG INPUT
Differential input voltage range
Differential input resistance (at dc), See Figure 97
2
2
V_PP
>1
>1
MΩ
Differential input capacitance, See Figure 98
3.5
3.5
pF
Analog Input Bandwidth
700
700
MHz
Analog Input common mode current (per input pin)
2
2
µA/MSPS
VCM Common mode output voltage
1.5
1.5
V
VCM output current capability
±4
±4
mA
DC ACCURACY
Offset error
–15
±2 15 –15
±2
15 mV
Temperature coefficient of offset error
0.005
0.005
mV/°C
Variation of offset error with supply
0.3
0.3
mV/V
E_GREF
Gain error due to internal reference inaccuracy alone
E_GCHAN Gain error of channel alone
Temperature coefficient of E_GCHAN
POWER SUPPLY
–1.25 ±0.2 1.25 –1.25 ±0.2 1.25 %FS
0.2
0.2
%FS
.001
.001
Δ%/°C
I_AVDD
Analog supply current
170
Output buffer supply current, LVDS interface with 100 Ω external
termination
70
I_DRVDD
Output buffer supply current, CMOS interface Fin = 3 MHz⁽¹⁾,
10-pF external load capacitance
56
155
mA
65
mA
48
mA
Analog power
561 630
510 570 mW
Digital power LVDS interface
Digital power CMOS interface, Fin = 3 MHz⁽²⁾, 10-pF external
load capacitance
126 160
101
118 153 mW
87
mW
Global power down
20 50
20
50 mW
Standby
120
120
mW
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the
supply voltage (see Figure 91 and CMOS interface power dissipation in application section).
(2) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10 pF.
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