ADS6149_1 Datasheet, PDF (10/69 Pages) Texas Instruments – 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs

ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com
TIMING REQUIREMENTS – LVDS AND CMOS MODES⁽¹⁾
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,
C_LOAD = 5pF⁽²⁾, R_LOAD = 100Ω⁽³⁾, LOW SPEED mode disabled, unless otherwise noted.
Min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to
1.9V.
PARAMETER
t_a
Aperture delay
t_j
Aperture jitter
Wake-up time
TEST CONDITIONS
The delay in time between the rising edge of the input sampling clock and
the actual time at which the sampling occurs
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of PDN GLOBAL mode
Time to valid data after stopping and restarting the input clock
ADC Latency⁽⁴⁾
Default, after reset
DDR LVDS MODE ⁽⁵⁾
t_su
Data setup time
t_h
Data hold time
t_PDI
Clock propagation delay
t_delay
LVDS bit clock duty cycle
Data valid ⁽⁶⁾ to zero-crossing of CLKOUTP
Zero-crossing of CLKOUT to data becoming invalid⁽⁶⁾
Input clock rising edge cross-over to output clock rising edge cross-over
100 MSPS ≤ Sampling frequency ≤ 250 MSPS
Duty cycle of differential clock, (CLKOUTP–CLKOUTM)
100 MSPS ≤ Sampling frequency ≤ 250 MSPS
t_RISE,
t_FALL
Data rise time,
Data fall time
Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
t_CLKRISE,
t_CLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
t_OE
Output enable (OE) to data delay
PARALLEL CMOS MODE⁽⁷⁾
t_START
t_DV
t_PDI
Input clock to data delay
Data valid time
Clock propagation delay
t_delay
Output clock duty cycle
Time to valid data after OE becomes active
Input clock rising edge cross-over to start of data valid⁽⁸⁾
Time interval of valid data⁽⁸⁾
Input clock rising edge cross-over to output clock rising edge cross-over
100 MSPS ≤ Sampling frequency ≤ 150 MSPS
Duty cycle of differential clock, (CLKOUT)
100 MSPS ≤ Sampling frequency ≤ 150 MSPS
t_RISE,
t_FALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD,
Fall time measured from 80% to 20% of DRVDD,
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
t_CLKRISE,
t_CLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD,
Fall time measured from 80% to 20% of DRVDD,
1 MSPS ≤ Sampling frequency ≤ 150 MSPS
t_OE
Output enable (OE) to data delay Time to valid data after OE becomes active
MIN TYP MAX UNIT
0.7 1.2 1.7 ns
170
fs rms
0.3
1
µs
25 100
10
clock
cycles
18
clock
cycles
0.8 1.2
ns
0.25 0.6
ns
0.2 × t_s + t_delay
ns
5.0 6.2 7.5 ns
52%
0.08 0.14 0.2 ns
0.08 0.14 0.2 ns
40
ns
3.2 ns
0.7 1.5
ns
0.78 × t_s + t_delay
5 6.5
8 ns
50%
0.7 1.2
2 ns
0.5
1 1.5 ns
20
ns
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground
(3) R_LOAD is the differential load resistance between the LVDS output pair.
(4) At higher frequencies, t_PDI is greater than one clock period and overall latency = ADC latency + 1.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to LOGIC HIGH of +100mV and LOGIC LOW of –100mV.
(7) For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).
(8) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V.
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