TAS1020A Datasheet, PDF (59/114 Pages) Texas Instruments – USB Streaming Controller

} Data Output By
Slave Device
SDA
} Data Output By
TAS1020A
SDA
MSB
Not Acknowledge
Acknowledge
SCL
S
1
2
8
9
Start Condition
Figure 2–13. TAS1020A Acknowledge on the I²C Bus
Clock Pulse For
Acknowledge
2.2.14.2 Single Byte Write
As shown is Figure 2–14, a single byte data write transfer begins with the master device transmitting a start condition
followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be a 0. After receiving the correct I²C device address and
the read/write bit, the I²C slave device responds with an acknowledge bit. Next, the TAS1020A transmits the address
byte or bytes corresponding to the I²C slave device internal memory address being accessed. After receiving the
address byte, the I²C slave device again responds with an acknowledge bit. Next, the TAS1020A device transmits
the data byte to be written to the memory address being accessed. After receiving the data byte, the I²C slave device
again responds with an acknowledge bit. Finally, the TAS1020A device transmits a stop condition to complete the
single byte data write transfer.
Start Condition
Acknowledge
Acknowledge
Acknowledge
SDA
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Memory or Register Address
Figure 2–14. Single Byte Write Transfer
Data Byte
Stop
Condition
2.2.14.3 Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are
transmitted by the TAS1020A device to the I²C slave device as shown in Figure 2–15. After receiving each data byte,
the I²C slave device responds with an acknowledge bit.
Start Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
SDA
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7 D6
D1 D0 ACK
D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Memory or Register Address
First Data Byte
Figure 2–15. Multiple Byte Write Transfer
Other
Last Data Byte
Data Bytes
Stop
Condition
2–45