TAS1020A Datasheet, PDF (105/114 Pages) Texas Instruments – USB Streaming Controller

A.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 – Address FFD5h)
The codec port receive interface configuration register3 is only used in I²S Mode 5.
Bit
Mnemonic
Type
Default
7
DDLY
R/W
0
6
TRSEN
R/W
0
5
CSCLKP
R/W
1
4
CSYNCP
R/W
1
3
CSYNCL
R/W
0
2
BYOR
R/W
0
1
CSCLKD
R/W
0
0
CSYNCD
R/W
0
BIT MNEMONIC
7 DDLY
6 TRSEN
5 CSCLKP
4 CSYNCP
3 CSYNCL
2 BYOR
1 CSCLKD
0 CSYNCD
NAME
Data delay
3-state enable
CSCLK polarity
CSYNC polarity
CSYNC length
Byte order
CSCLK direction
CSYNC direction
DESCRIPTION
The data delay bit is set to 1 by the MCU to program a one SCLK2 cycle delay of the serial data
output and input signals in reference to the leading edge of the LRCK2 signal. The MCU must
clear this bit to a 0 for no delay between these signals.
The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the serial data output
signal to the high-impedance state for time slots during the audio frame that are not valid. The
MCU must clear this bit to a 0 to program the hardware to use zero-padding for the serial data
output signal for time slots during the audio frame that are not valid.
The CSCLKP polarity bit is used by the MCU to program the clock edge used for the codec port
interface frame sync (LRCK2) output signal and codec port interface serial data input (CDAT1)
signal. When this bit is set to a 1, the LRCK2 signal is generated with the negative edge of the
codec port interface serial clock (SCLK2) signal. Also, when this bit is set a 1, the CDATI signal is
sampled with the positive edge of the SCLK2 signal. When this bit is cleared to 0, the LRCK2
signal is generated with the positive edge of SCLK2 and the CDATI signal is sampled with the
negative edge of the SCLK2 signal.
The CSYNCP polarity bit is set to a 1 by the MCU to program the polarity of the codec port interface
frame sync (LRCK2) output signal to be active high. The MCU must clear this bit to a 0 to program
the polarity of the LRCK2 output signal to be active low.
The CSYNCL polarity bit is set to a 1 by the MCU to program the length of the codec port interface
frame sync (LRCK2) output signal to be the same number of SCLK2 cycles as time slot 0. The
MCU must clear this bit to a 0 to program the length of the LRCK2 output signal to be one SCLK2
cycle.
The byte order bit is used by the MCU to program the byte order for the data moved by the DMA
between the USB endpoint buffer and the codec port interface. When this bit is set to a 1, the byte
order of each audio sample is reversed when the data is moved to/from the USB endpoint buffer.
When this bit is cleared to a 0, the byte order of the each audio sample is unchanged.
The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec port
interface serial clock (SCLK2) signal as an input of the TAS1020A device. The MCU must clear
this bit to a 0 to program the direction of the CSCLK signal as an output from the TAS1020A device.
The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec port
interface frame sync (LRCK2) signal as an input of the TAS1020A device. The MCU must clear
this bit to a 0 to program the direction of the LRCK2 signal as an output from the TAS1020A device.
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