TAS1020A Datasheet, PDF (109/114 Pages) Texas Instruments – USB Streaming Controller

A.5.7 Miscellaneous Registers
This section describes the memory-mapped registers used for the control and operation of miscellaneous functions
in the TAS1020A device. The registers include the USB OUT endpoint interrupt register, the USB IN endpoint interrupt
register, the interrupt vector register, the global control register, and the memory configuration register.
A.5.7.1 USB OUT endpoint Interrupt Register (OEPINT – Address FFB4h)
The USB OUT endpoint interrupt register contains the interrupt pending status bits for the USB OUT endpoints. These
bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for
diagnostic purposes only.
Bit
Mnemonic
Type
Default
7
OEPI7
R
0
6
OEPI6
R
0
5
OEPI5
R
0
4
OEPI4
R
0
3
OEPI3
R
0
2
OEPI2
R
0
1
OEPI1
R
0
0
OEPI0
R
0
BIT MNEMONIC
NAME
7:0 OEPI(7:0)
OUT endpoint interrupt
DESCRIPTION
The OUT endpoint interrupt status bit for a particular USB OUT endpoint is set to a 1 by the
UBM when a successful completion of a transaction occurs to that OUT endpoint. When a
bit is set, an interrupt to the MCU is generated and the corresponding interrupt vector
results. The status bit is cleared when the MCU writes to the interrupt vector register. These
bits do not apply to isochronous OUT endpoints.
A.5.7.2 USB IN endpoint Interrupt Register (IEPINT – Address FFB3h)
The USB IN endpoint interrupt register contains the interrupt pending status bits for the USB IN endpoints. These
bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and are used for
diagnostic purposes only.
Bit
Mnemonic
Type
Default
7
IEPI7
R
0
6
IEPI6
R
0
5
IEPI5
R
0
4
IEPI4
R
0
3
IEPI3
R
0
2
IEPI2
R
0
1
IEPI1
R
0
0
IEPI0
R
0
BIT MNEMONIC
NAME
7:0 IEPI(7:0)
IN endpoint interrupt
DESCRIPTION
The IN endpoint interrupt status bit for a particular USB IN endpoint is set to a 1 by the UBM
when a successful completion of a transaction occurs to that IN endpoint. When a bit is set,
an interrupt to the MCU is generated and the corresponding interrupt vector results. The
status bit is cleared when the MCU writes to the interrupt vector register. These bits do not
apply to isochronous IN endpoints.
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