TMS320VC5510 Datasheet, PDF (58/86 Pages) Texas Instruments – Digital Signal Processor

Electrical Specifications
CLKOUT^§
CEx^¶
BE[3:0]
Setup = 1^†
A1
A2
Strobe = 5^†
Not ready = 2
Extended
Hold = 1^† Hold = 2^†‡
A1
A3
A4
A5
A[21:0]
A12
A13
D[31:0]
AOE
ARE
AWE
ARDY^#
A14
A14
A11
A10
A11
A10
† _{Setup, Strobe, Hold, and Extended Hold are programmable in the EMIF. The programmable Hold period is not associated with the activity of}
the HOLD and HOLDA signals.
‡ _{The extended hold time is programmable in the EMIF and is only present when consecutive memory accesses are made to different CEx spaces,}
or are of different types (read/write).
§ _{All timings referenced to CLKOUT assume CLKOUT is the same frequency as the internal CPU clock (divide-by-1 mode).}
¶ _{The chip enable that becomes active depends on the address.}
# _{ARDY is synchronized internally. If the setup time shown is not met, ARDY will be recognized on the next clock cycle.}
Figure 5−5. Asynchronous Memory Write Timing
58 SPRS076J
June 2000 − Revised July 2004