TMS320VC5510 Datasheet, PDF (28/86 Pages) Texas Instruments – Digital Signal Processor

Functional Overview
3.2.2 Direct Memory Access (DMA)
The 5510 DMA provides the following features:
• Four standard ports, one for each of the following data resources: DARAM, SARAM, Peripherals, and
External Memory
• Six channels, which allow the DMA controller to track the context of six independent DMA channels
• Programmable low/high priority for each DMA channel
• One interrupt for each DMA channel
• Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected
events.
• Programmable address modification for source and destination addresses
• Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software
control.
• DMA controller supports EHPI accesses to internal/external memory
The 5510 DMA controller allows transfers to be synchronized to selected events. The 5510 supports
14 separate sync events and each channel can be tied to separate sync events independent of the other
channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel
Control Register (DMA_CCR). The sync events available on the 5510 are shown in Table 3−6.
For more information on the 5510 DMA, see the TMS320VC5503/5507/5509/5510 DSP Direct Memory
Access (DMA) Controller Reference Guide (literature number SPRU587).
Table 3−6. DMA Sync Events
SYNC FIELD IN DMA_CCR
00000b
00001b
00010b
00101b
00110b
01001b
01010b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
Other values
SYNC EVENT
No sync event
McBSP0 receive event (REVT0)
McBSP0 transmit event (XEVT0)
McBSP1 receive event (REVT1)
McBSP1 transmit event (XEVT1)
McBSP2 receive event (REVT2)
McBSP2 transmit event (XEVT2)
Timer 0 event
Timer 1 event
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Reserved (do not use these values)
28 SPRS076J
June 2000 − Revised July 2004