TMS320VC5510 Datasheet, PDF (54/86 Pages) Texas Instruments – Digital Signal Processor

Electrical Specifications
5.7 Clock Options
This section provides the timing requirements and switching characteristics for the various clock options
available on the 5510.
5.7.1 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of one, two, or four
to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock mode
register. The contents of this field only affect clock generation while the device is in bypass mode. In this mode,
the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−3 and Table 5−4 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5−2).
Table 5−3. CLKIN in Bypass Mode Timing Requirements
VC5510-160 VC5510-200
NO.
UNIT
MIN MAX MIN MAX
C7 t_c(CI)
C8 t_f(CI)
C9 t_r(CI)
Cycle time, CLKIN
Fall time, CLKIN
Rise time, CLKIN
20
†
20
† ns
6
6 ns
6
6 ns
C10 t_w(CIL) Pulse duration, CLKIN low
4
4
ns
C11 t_w(CIH) Pulse duration, CLKIN high
4
4
ns
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz.
Table 5−4. CLKOUT in Bypass Mode Switching Characteristics
NO.
PARAMETER
C1 t_c(CO)
Cycle time, CLKOUT
C2 t_d(CI-CO)
Delay time, CLKIN high/low to CLKOUT high/low
C3 t_f(CO)
Fall time, CLKOUT
C4 t_r(CO)
Rise time, CLKOUT
C5 t_w(COL)
Pulse duration, CLKOUT low
C6 t_w(COH)
Pulse duration, CLKOUT high
‡ _{N = Clock frequency synthesis factor}
VC5510-160
MIN
TYP MAX
20 t_c(CI)/N^‡
1
7
14
1
1
H−1
H+1
H−1
H+1
VC5510-200
MIN
TYP MAX
20 t_c(CI)/N^‡
1
7
14
1
1
H−1
H+1
H−1
H+1
UNIT
ns
ns
ns
ns
ns
ns
C7
CLKIN
C11
C10
C9
C8
CLKOUT
C1
C2
C3
C4
C6
C5
NOTE A: The relationship of CLKIN to CLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 5−2 is intended
to illustrate the timing parameters only and may differ based on configuration.
Figure 5−2. Bypass Mode Clock Timing
54 SPRS076J
June 2000 − Revised July 2004