ADS6124IRHB25 Datasheet, PDF (58/67 Pages) Texas Instruments – 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
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AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ΔV_SUP is the change in the
supply voltage and ΔV_OUT is the resultant change in the ADC output code (referred to the input), then
PSRR = 20Log¹⁰
DV_OUT
DV_SUP
(Expressed in dBc)
(8)
Common Mode Rejection Ratio (CMRR)
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is the
change in the input common-mode voltage and ΔV_OUT is the resultant change in the ADC output code (referred
to the input), then
CMRR = 20Log¹⁰
DV_OUT
DV_CM
(Expressed in dBc)
(9)
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
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