ADS6124IRHB25 Datasheet, PDF (32/67 Pages) Texas Instruments – 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
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TYPICAL CHARACTERISTICS - ADS6123 (F_S= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
100
96
92
88
Gain = 3.5 dB
84
80
76
Gain = 0 dB
72
68
64
60
0 50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G043
Figure 50.
SFDR vs INPUT FREQUENCY ACROSS GAINS
95
Input adjusted to get −1dBFS input
90
3 dB
85
2 dB 6 dB
80
0 dB
75
1 dB
5 dB
4 dB
70
65
60
0
100
200
300
400
f_IN − Input Frequency − MHz
Figure 52.
500
G045
PERFORMANCE vs AVDD
88
f_IN = 70.1 MHz
86 _{DRVDD = 3.3 V}
SFDR
84
82
80
78
76
SNR
74
72
3.0
3.1
3.2
3.3
3.4
3.5
AV_DD − Supply Voltage − V
Figure 54.
78
77
76
75
74
73
72
71
70
3.6
G047
SNR vs INPUT FREQUENCY (LVDS interface)
76
74
72
Gain = 0 dB
70
68
Gain = 3.5 dB
66
64
62
0
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G044
Figure 51.
SINAD vs INPUT FREQUENCY ACROSS GAINS
74
72
0 dB ^{Input adjusted to get −1dBFS input}
1 dB
70
2 dB
3 dB
68
66
64
4 dB _{5 dB}
62
6 dB
60
58
0
100
200
300
400
f_IN − Input Frequency − MHz
Figure 53.
500
G046
PERFORMANCE vs DRVDD
102
74
f_IN = 10.1 MHz
100 AV_DD = 3.3 V
73
SNR
98
72
96
71
94
70
SFDR
92
69
90
68
88
67
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DRV_DD − Supply Voltage − V
G048
Figure 55.
32
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