English
Language : 

MSC1200 Datasheet, PDF (57/60 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory
◁
One Microsecond Register (USEC)
7
6
5
SFR FBH
0
0
FREQ5
4
FREQ4
3
FREQ3
2
FREQ2
1
FREQ1
0
FREQ0
Reset Value
03H
FREQ5-0 Clock Frequency – 1. This value + 1 divides the system clock to create a 1µs Clock.
bits 5-0
USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFH).
One Millisecond Low Register (MSECL)
SFR FCH
7
MSECL7
6
MSECL6
5
MSECL5
4
MSECL4
3
MSECL3
2
MSECL2
1
MSECL1
0
MSECL0
Reset Value
9FH
MSECL7-0 One Millisecond Low. This value in combination with the next register is used to create a 1ms Clock.
bits 7-0
1ms Clock = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFH).
One Millisecond High Register (MSECH)
SFR FDH
7
MSECH7
6
MSECH6
5
MSECH5
4
MSECH4
3
MSECH3
2
MSECH2
1
MSECH1
0
MSECH0
Reset Value
0FH
MSECH7-0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock.
bits 7-0
1ms = (MSECH • 256 + MSECL + 1) • tCLK.
One Hundred Millisecond Register (HMSEC)
SFR FEH
7
HMSEC7
6
HMSEC6
5
HMSEC5
4
HMSEC4
3
HMSEC3
2
HMSEC2
1
HMSEC1
0
HMSEC0
HMSEC7-0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.
bits 7-0
100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK.
Reset Value
63H
Watchdog Timer Register (WDTCON)
SFR FFH
7
EWDT
6
DWDT
5
RWDT
4
WDCNT4
3
WDCNT3
2
WDCNT2
1
WDCNT1
0
WDCNT0
Reset Value
00H
EWDT
bit 7
Enable Watchdog (R/W).
Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT
bit 6
Disable Watchdog (R/W).
Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT
bit 5
Reset Watchdog (R/W).
Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4-0 Watchdog Count (R/W).
bits 4-0
Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There
is an uncertainty of 1 count.
NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared
and the watchdog timer expires, an interrupt is generated (see Table VII).
MSC1200
57
SBAS289E
www.ti.com
 ▷