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MSC1200 Datasheet, PDF (51/60 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory
SSCON1-0 Summation/Shift Control.
bits 7-6
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0
SHF2
SHF1
SHF0 DESCRIPTION
0
0
0
0
0
0
0
0
Clear Summation Register
0
0
0
1
0
0
0
0
CPU Summation on Write to SUMR0
0
0
1
0
0
0
0
0
CPU Subtraction on Write to SUMR0
1
0
x
x
x
Note (1) Note (1) Note (1) CPU Shift Only
0
1
Note (1) Note (1) Note (1)
x
x
x
ADC Summation Only
1
1
Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation Completes then Shift Completes
NOTES: (1) Refer to register bit definition.
SCNT2-0
bits 5-3
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
SUMR0 register clears the interrupt.
SCNT2 SCNT1 SCNT0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SUMMATION COUNT
2
4
8
16
32
64
128
256
SHF2-0
bits 2-0
Shift Count.
SHF2
0
0
0
0
1
1
1
1
SHF1
0
0
1
1
0
0
1
1
SHF0
0
1
0
1
0
1
0
1
SHIFT
1
2
3
4
5
6
7
8
DIVIDE
2
4
8
16
32
64
128
256
Summation Register 0 (SUMR0)
7
6
SFR E2H
5
4
3
2
1
0
Reset Value
LSB
00H
SUMR0
bits 7-0
Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7.
Write: will cause values in SUMR3-0 to be added to or subtracted from the summation register.
Read: will clear the Summation Interrupt.
Summation Register 1 (SUMR1)
7
6
SFR E3H
5
4
3
2
1
0
Reset Value
00H
SUMR1
bits 7-0
Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15.
Summation Register 2 (SUMR2)
7
6
SFR E4H
5
4
3
2
1
0
Reset Value
00H
SUMR2
bits 7-0
Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23.
Summation Register 3 (SUMR3)
7
6
SFR E5H
MSB
5
4
3
2
1
0
Reset Value
00H
SUMR3
bits 7-0
Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31.
MSC1200
51
SBAS289E
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