MSC1200 Datasheet, PDF (41/60 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

Auxiliary Interrupt Status Register (AISTAT)
7
6
5
4
3
2
1
0
SFR A7_H
SEC
SUM
ADC
MSEC
I2C
CNT
ALVD
0
Reset Value
00_H
SEC
bit 7
SUM
bit 6
ADC
bit 5
Second System Timer Interrupt Status Flag (lowest priority AI).
0: SEC Interrupt cleared or masked.
1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9_H).
Summation Register Interrupt Status Flag.
0: SUM Interrupt cleared or masked.
1: SUM Interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2_H).
ADC Interrupt Status Flag.
0: ADC Interrupt cleared or masked.
1: ADC Interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9_H; if active, no new data will be
written to the ADC Results registers).
MSEC
bit 4
Millisecond System Timer Interrupt Status Flag.
0: MSEC Interrupt cleared or masked.
1: MSEC Interrupt active (it is cleared by reading MSINT, SFR FA_H).
I2C
bit 3
I²C Start/Stop Interrupt Status Flag.
0: I²C Start/stop Interrupt cleared or masked.
1: I²C Start/stop Interrupt active (it is cleared by writing to I2CDATA, SFR 9B_H).
CNT
bit 2
CNT Interrupt Status Flag.
0: CNT Interrupt cleared or masked.
1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9B_H).
ALVD
Analog Low Voltage Detect Interrupt Status Flag.
bit 1
0: ALVD Interrupt cleared or masked.
1: ALVD Interrupt active (cleared in HW if AV_DD exceeds ALVD threshold).
NOTE: If an interrupt is masked, the status can be read in AIPOL, SFR A4_H.
7
6
SFR A8_H
EA
0
5
4
3
2
1
0
Reset Value
0
ES0
ET1
EX1
ET0
EX0
00_H
Interrupt Enable (IE)
EA
Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6_H).
bit 7
0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register.
1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
ES0
Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt.
bit 4
0: Disable all serial Port 0 interrupts.
1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98_H) or TI_0 (SCON0.1, SFR 98_H) flags.
ET1
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
bit 3
0: Disable Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88_H).
EX1
bit 2
Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 pin.
ET0
Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
bit 1
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88_H).
EX0
bit 0
Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 pin.
MSC1200
41
SBAS289E
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