TMS320C6713B Datasheet, PDF (54/153 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
Terminal Functions (Continued)
SIGNAL
PIN NO.
TYPE†
IPD/
IPU‡
DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)
GP[4](EXT_INT4)/
AMUTEIN1
1
C2
I/O/Z
IPU
General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or
McASP1 mute input (I/O/Z).
HD3/AMUTE1
154
C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).
HRDY/ACLKR1
140
H19 I/O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
HD6/AHCLKR1
161
C17
I/O/Z
IPU
Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master
clock (I/O/Z).
HAS/ACLKX1
153
E18 I/O/Z IPU Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z).
HD5/AHCLKX1
159
B18
I/O/Z
IPU
Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency
master clock (I/O/Z).
HHWIL/AFSR1
Host half-word select − first or second half-word (not necessarily high or low
139
H20 I/O/Z IPU order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK)
(I/O/Z).
HD2/AFSX1
155
D18
I/O/Z
IPU
Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/
right clock (LRCLK) (I/O/Z).
HD1/AXR1[7]
152
D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 TX/RX data pin 7 (I/O/Z).
HDS1/AXR1[6]
151
E19 I/O/Z IPU Host data strobe 1 (I) [default] or McASP1 TX/RX data pin 6 (I/O/Z).
HDS2/AXR1[5]
150
F18 I/O/Z IPU Host data strobe 2 (I) [default] or McASP1 TX/RX data pin 5 (I/O/Z).
HD0/AXR1[4]
147
E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 TX/RX data pin 4 (I/O/Z).
HCNTL0/AXR1[3]
Host control − selects between control, address, or data registers (I) [default] or
146
G18
I/O/Z
IPU _{McASP1 TX/RX data pin 3 (I/O/Z).}
HCS/AXR1[2]
145
F20 I/O/Z IPU Host chip select (I) [default] or McASP1 TX/RX data pin 2 (I/O/Z).
HCNTL1/AXR1[1]
144
G19
I/O/Z
IPU
Host control − selects between control, address, or data registers (I) [default] or
McASP1 TX/RX data pin 1 (I/O/Z).
HR/W/AXR1[0]
143
G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)
GP[5](EXT_INT5)/
AMUTEIN0
6
C1
I/O/Z
IPU
General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or
McASP0 mute input (I/O/Z).
CLKX1/AMUTE0
33
L3
I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
CLKR0/ACLKR0
19
H3
I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This
TINP1/AHCLKX0
12
F2
I/O/Z IPD pin defaults as Timer 1 input (I) and McASP transmit high−frequency master
clock input (I).
CLKX0/ACLKX0
16
G3
I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).
CLKS0/AHCLKR0
28
K3
I/O/Z
IPD
McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0
receive high-frequency master clock (I/O/Z).
FSR0/AFSR0
McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or
24
J3
I/O/Z
IPD _{left/right clock (LRCLK) (I/O/Z).}
FSX0/AFSX0
21
H1
I/O/Z
IPD
McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync
or left/right clock (LRCLK) (I/O/Z).
FSR1/AXR0[7]
38
M3
I/O/Z
IPD
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7
(I/O/Z).
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors}
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
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