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TMS320C6713B Datasheet, PDF (113/153 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles† (see Figure 40)
PYP-200,-225
GDP/ZDP -225, -300
NO.
PYPA -167, -200
UNIT
GDPA/ZDPA −200
MIN MAX
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high
1.5
ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high
2.5
ns
† The C6713B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 40−Figure 46)
PYP-200,-225
GDP/ZDP -225, -300
NO.
PARAMETER
PYPA -167, -200
UNIT
GDPA/ZDPA −200
MIN MAX
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid
1.5
7 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid
7 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid
1.5
ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid
7 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid
1.5
ns
8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid
1.5
7 ns
9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid
7 ns
10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid
1.5
ns
11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid
1.5
7 ns
12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid
1.5
7 ns
† The C6713B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
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